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    Subject[PATCH v2 0/4] ST PLL improvement
    Date
    Changes in v2:
    - Add const for st_pll4600c28_418_a9 structure
    - Use readl_relaxed_poll_timeout macro instead Jiffies
    - Add patch to enable stih418 A9 pll via DT.

    This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3'

    Gabriel Fernandez (4):
    drivers: clk: st: Support for enable/disable in Clockgen PLLs
    drivers: clk: st: PLL rate change implementation for DVFS
    drivers: clk: st: Correct the pll-type for A9 for stih418
    ARM: STi: DT: Add support for stih418 A9 pll

    .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 +
    arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
    drivers/clk/st/clkgen-mux.c | 3 +
    drivers/clk/st/clkgen-pll.c | 469 ++++++++++++++++++++-
    drivers/clk/st/clkgen.h | 2 +
    5 files changed, 468 insertions(+), 9 deletions(-)

    --
    1.9.1



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