Messages in this thread | | | From | Robert Jarzmik <> | Subject | Re: [PATCH] mtd: nand: pxa3xx-nand: fix random command timeouts | Date | Mon, 17 Aug 2015 00:18:09 +0200 |
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Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> writes:
> On 12 Aug 06:22 PM, Robert Jarzmik wrote: > > This fix looks correct. Thanks! > > Couple questions: > > 1. In which platform are you seeing this bug? zylonite with a pxa310 (ie. internal stacked NAND).
> 2. Is this a regression? (i.e. should we queue it for -stable?) No, it's been there for ages I think.
> Also, one might question why we can't just write NDSR right after it's read, > before we wake the IRQ thread or start DMA. It appears this is > a requirement of BCH, as per the comment in drain_fifo. For irq thread that won't make any difference, the irq handler will finish first and clear the bits anyway. For DMA it's better.
And more generaly speaking, I like it better, to clear it once read.
> It would be nice to put a comment explaining why we clear NDSR only > before the check to WRCMDREQ. Maybe even copy-pasting something > from the commit log? If we move it up to something like that : status = nand_readl(info, NDSR); nand_writel(info, NDSR, status); Then the comment is overkill I think.
> I'd like to say "Yay, let's pick it" but I'd like to make sure this is > tested on all platforms first (unless you've tested it already). I tested on zylonite (where bug occurs) and cm-x300 (where bug never occurs).
Cheers.
-- Robert
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