lkml.org 
[lkml]   [2015]   [Aug]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH v10 3/8] add fpga manager core
On Fri, 14 Aug 2015, Moritz Fischer wrote:

> Hi Alan,
>
> I've updated my Zynq driver (it can be found in an older version
> against your v8 in the Xilinx tree, too)
>
> https://github.com/mfischer/linux/tree/alan-fpga-mgr-v10

Since we are both already using this and have been for a while now, I hope it
can go up into the mainstream instead of continuing to exist only in Altera
and Xilinx's git trees.

>
> to use your v10 version of the patch. Either I'm using the API wrong ,
> or it never gets to the 'operating state'.

I'm sure you are doing it right.

> > + }
> > +
> > + /*
> > + * After all the FPGA image has been written, do the device specific
> > + * steps to finish and set the FPGA into operating mode.
> > + */
> > + mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
> > + ret = mgr->mops->write_complete(mgr, flags);
> > + if (ret) {
> > + dev_err(dev, "Error after writing image data to FPGA\n");
> > + mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
> > + return ret;
> > + }
> Maybe I'm misunderstanding something here. Shouldn't we set mgr->state
> = FPGA_MGR_STATE_OPERATING
> here, seen that the _show function below uses the mgr->state?

The FPGA gets programmed, but state wasn't getting updated.
Should have "mgr->state = FPGA_MGR_STATE_OPERATING" here.
Will add in v11.

Thanks for the review and the ack. If you see anything else that seems
wrong, please let me know.

Alan


\
 
 \ /
  Last update: 2015-08-14 17:01    [W:0.108 / U:0.316 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site