Messages in this thread | | | Date | Wed, 29 Jul 2015 21:33:27 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [PATCH v3 0/3] x86/pci/intel-mid-pci: fix to get eMMC detected |
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On Wed, 29 Jul 2015, Andy Shevchenko wrote:
> On Intel Edison we have an interesting implementation of x86 platform without > legacy PIC and with specific PCI. There are devices which are not using > interrupt line 0, but have it assigned in the PCI configuration. By default > first come gets it, though the first eMMC host controller is the actual user > for IRQ0. > > So, this series provides a quirk (patch 1) to resolve the issue, a small fix of > error code (patch 2), and a sparse warning fix (patch 3). > > Changelog v3: > - address Thomas' comments > - massage changelog (what Thomas proposed) > > Andy Shevchenko (3): > x86/pci/intel_mid_pci: work around for IRQ0 assignment > x86/pci/intel_mid_pci: propagate actual return code > x86/pci/intel_mid_pci: fix a sparse warning
I've picked them up. If you get the tip-bot mails, you might notice a few edits on the changelogs.
- Sentence starts with an upper case letter.
- You cannot fix a sparse warning.
- "This patch does ...." is just horrible. When one reads a patch he already knows that it is a patch.
Please avoid these things in the future.
Thanks,
tglx
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