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SubjectRe: [PATCH 1/1] perf/x86: Add Intel power cstate PMUs support
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On Fri, Jul 24, 2015 at 1:57 PM, Liang, Kan <kan.liang@intel.com> wrote:
>> > + * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
>> > + * perf code: 0x06
>> > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW
>> > + * Scope: Package (physical package)
>> > + * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
>> > + * perf code: 0x07
>> > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW
>> > + * Scope: Package (physical package)
>> > + * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
>> > + * perf code: 0x08
>> > + * Available model: HSW ULT only
>> > + * Scope: Package (physical package)
>> > + * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
>> > + * perf code: 0x09
>> > + * Available model: HSW ULT only
>> > + * Scope: Package (physical package)
>> > + * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
>> > + * perf code: 0x0a
>> > + * Available model: HSW ULT only
>> > + * Scope: Package (physical package)
>> > + * MSR_SLM_PKG_C6_RESIDENCY: Package C6 Residency Counter for
>> SLM.
>> > + * perf code: 0x0b
>> > + * Available model: SLM,AMT
>> > + * Scope: Package (physical package)
>> > + *
>> > + */
>> > +
>> Why would the user (and the tools) have to change the event code to
>> measure, let's say C6 residency, between SLM (0xb) and and BDW (0x6)?
>> Are they not measuring the same thing?
>>
>
> Yes, they are measuring the same thing, but with different MSR.
> I will make their event code consistent and special handle PKG_C6
> in event_init in next version.
>
The user should not be concerned with the MSR mapping. The user should
only see the event name and understand what it measures. The kernel should
take care of mapping the event to the correct MSR as per perf_events design.

>
> Thanks,
> Kan


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