Messages in this thread Patch in this message | | | From | Andy Lutomirski <> | Subject | [PATCH 2/5] x86/entry/64, entry: Set up a valid sysenter stack and prepare for 32-bit merge | Date | Thu, 23 Jul 2015 08:31:40 -0700 |
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Oddly, 64-bit kernels already allocate a percpu sysenter stack, but they don't enable it. Enable the stack and tweak the rest of the sysenter setup code to be similar to the 32-bit version.
This eliminates the only place in the kernel in which TF could be set without a valid stack.
Signed-off-by: Andy Lutomirski <luto@kernel.org> --- arch/x86/kernel/cpu/common.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9b3a43583f81..fba86ed46aa6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1193,9 +1193,11 @@ void syscall_init(void) * This does not cause SYSENTER to jump to the wrong location, because * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). */ - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); + wrmsrl_safe(MSR_IA32_SYSENTER_CS, __KERNEL_CS); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, + (unsigned long)&per_cpu(cpu_tss, smp_processor_id()) + + offsetofend(struct tss_struct, SYSENTER_stack)); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_compat); #else wrmsrl(MSR_CSTAR, ignore_sysret); wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); -- 2.4.3
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