Messages in this thread | | | Date | Fri, 17 Jul 2015 17:47:53 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings |
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On 07/10, James Liao wrote: > Avoid u32 overflow when calculate post divider setting, and > increase the max post divider setting from 3 (/8) to 4 (/16). > > Signed-off-by: James Liao <jamesjj.liao@mediatek.com> > ---
Applied to clk-next
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