Messages in this thread | | | Date | Fri, 17 Jul 2015 16:31:00 -0700 | From | Andi Kleen <> | Subject | Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake |
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On Fri, Jul 17, 2015 at 03:00:18PM -0700, Stephane Eranian wrote: > Andi, > > On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen <ak@linux.intel.com> wrote: > >> But then, the SDM is misleading. It is not describing what's > >> implemented for SKL. > > > > Actually it has a list of valid values you can put into the various fields. > > None of them have the bits set you're trying to set. > > > You are talking about the events (bit 0-7). I am talking about the bubble > thresholds. I am okay with the event list for bits 0-7.
Fair enough. There's a one-off in the MSR table and table 18-54. The IDQ bubble width is only 21:20. I'll ask for that to be fixed in both places that document them.
Thanks.
-Andi
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