Messages in this thread |  | | Date | Sat, 18 Jul 2015 00:23:01 +0200 (CEST) | | From | Thomas Gleixner <> | | Subject | Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake |
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On Fri, 17 Jul 2015, Andi Kleen wrote: > On Fri, Jul 17, 2015 at 11:05:37PM +0200, Peter Zijlstra wrote: > > On Fri, Jul 17, 2015 at 10:52:33PM +0200, Andi Kleen wrote: > > > > > > I don't think the code is the right place to document such registers. > > > > If the code deviates from the SDM, it _is_ the right place to explain, > > seeing how its the only place. > > It won't anymore in the next revision.
And that justifies to leave completely undocumented crap in the code for the current revision?
> ak@linux.intel.com -- Speaking for myself only
I'm sure Intel appreciates that disclaimer.
Thanks,
tglx
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