Messages in this thread |  | | Date | Fri, 17 Jul 2015 13:41:04 -0700 | | Subject | Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake | | From | Stephane Eranian <> |
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Andi,
On Fri, Jul 17, 2015 at 1:09 PM, Andi Kleen <ak@linux.intel.com> wrote: >> I believe this mask of 0x3fff17 is wrong and should instead be >> 0x7fffff based on the description of the FRONTEND >> MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some >> valid latency values may be rejected. > > No, my mask is correct. > Ok, so your event mask (0x17) really only allows what's defined instead the full width of the field.
As for the IDQ_BUBBLE_WIDTH, you only allow 2 bits out of 3, so maximum bubble threshold is 3 instead of 7. I assume this is because you know that it cannot have more than 3 simultaneously then.
Would be good to explain this a bit more in the code.
> -- > ak@linux.intel.com -- Speaking for myself only
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