Messages in this thread | | | Date | Wed, 15 Jul 2015 17:01:46 +0100 | From | Mark Brown <> | Subject | Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller |
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On Wed, Jul 15, 2015 at 02:12:54PM +0000, Ranjit Abhimanyu Waghmode wrote:
> > > What is stacked mode? > > > --------------------- > > > ZynqMP GQSPI controller supports stacked mode with following > > functionalities: > > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > > in a shared bus arrangement to reduce IO pin count. > > > 2) Separate chip select lines > > > 3) Shared I/O lines > > > 4) This mode is targeted for increasing the flash memory and no performance > > > improvement when compared with single.
> > This is just a normal SPI controller from a SPI point of view.
> How can we really represent the stacked mode in current configuration?
In the same way as any other controller with two chip selects... there are quite a few other drivers that provide examples of this, you should look for one that has hardware control similar to yours. [unhandled content-type:application/pgp-signature] | |