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    Subject[PATCH 3.16.y-ckt 121/185] drm/radeon: compute ring fix hibernation (CI GPU family) v2.
    Date
    3.16.7-ckt15 -stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com>

    commit 161569deaa03cf3c00ed63352006193f250b0648 upstream.

    In order for hibernation to reliably work we need to cleanup more
    thoroughly the compute ring. Hibernation is different from suspend
    resume as when we resume from hibernation the hardware is first
    fully initialize by regular kernel then freeze callback happens
    (which correspond to a suspend inside the radeon kernel driver)
    and turn off each of the block. It turns out we were not cleanly
    shutting down the compute ring. This patch fix that.

    Hibernation and suspend to ram were tested (several times) on :
    Bonaire
    Hawaii
    Mullins
    Kaveri
    Kabini

    Changed since v1:
    - Factor the ring stop logic into a function taking ring as arg.

    Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Luis Henriques <luis.henriques@canonical.com>
    ---
    drivers/gpu/drm/radeon/cik.c | 34 ++++++++++++++++++++++++++++++++++
    1 file changed, 34 insertions(+)

    diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
    index 0cf54a4b83bd..6bdaa9500f78 100644
    --- a/drivers/gpu/drm/radeon/cik.c
    +++ b/drivers/gpu/drm/radeon/cik.c
    @@ -4245,6 +4245,31 @@ void cik_compute_set_wptr(struct radeon_device *rdev,
    WDOORBELL32(ring->doorbell_index, ring->wptr);
    }

    +static void cik_compute_stop(struct radeon_device *rdev,
    + struct radeon_ring *ring)
    +{
    + u32 j, tmp;
    +
    + cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
    + /* Disable wptr polling. */
    + tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
    + tmp &= ~WPTR_POLL_EN;
    + WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
    + /* Disable HQD. */
    + if (RREG32(CP_HQD_ACTIVE) & 1) {
    + WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
    + for (j = 0; j < rdev->usec_timeout; j++) {
    + if (!(RREG32(CP_HQD_ACTIVE) & 1))
    + break;
    + udelay(1);
    + }
    + WREG32(CP_HQD_DEQUEUE_REQUEST, 0);
    + WREG32(CP_HQD_PQ_RPTR, 0);
    + WREG32(CP_HQD_PQ_WPTR, 0);
    + }
    + cik_srbm_select(rdev, 0, 0, 0, 0);
    +}
    +
    /**
    * cik_cp_compute_enable - enable/disable the compute CP MEs
    *
    @@ -4258,6 +4283,15 @@ static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
    if (enable)
    WREG32(CP_MEC_CNTL, 0);
    else {
    + /*
    + * To make hibernation reliable we need to clear compute ring
    + * configuration before halting the compute ring.
    + */
    + mutex_lock(&rdev->srbm_mutex);
    + cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
    + cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
    + mutex_unlock(&rdev->srbm_mutex);
    +
    WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
    rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
    rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;

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