Messages in this thread Patch in this message | | | From | Andy Shevchenko <> | Subject | [PATCH v5 7/8] clk: bcm: switch to GENMASK() | Date | Mon, 13 Jul 2015 17:07:47 +0300 |
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Convert the code to use GENMASK() helper instead of custom approach.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- drivers/clk/bcm/clk-iproc-asiu.c | 22 ++++++++-------------- drivers/clk/bcm/clk-iproc-pll.c | 31 ++++++++++++++----------------- drivers/clk/bcm/clk-iproc.h | 1 - drivers/clk/bcm/clk-kona-setup.c | 2 +- drivers/clk/bcm/clk-kona.c | 12 +++--------- 5 files changed, 26 insertions(+), 42 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c index f630e1b..0db9c2b 100644 --- a/drivers/clk/bcm/clk-iproc-asiu.c +++ b/drivers/clk/bcm/clk-iproc-asiu.c @@ -96,9 +96,11 @@ static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw, } /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */ - div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); + div_h = val >> clk->div.high_shift; + div_h &= GENMASK(clk->div.high_width - 1, 0); div_h++; - div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); + div_l = val >> clk->div.low_shift; + div_l &= GENMASK(clk->div.low_width - 1, 0); div_l++; clk->rate = parent_rate / (div_h + div_l); @@ -155,20 +157,12 @@ static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate, val = readl(asiu->div_base + clk->div.offset); val |= 1 << clk->div.en_shift; - if (div_h) { - val &= ~(bit_mask(clk->div.high_width) - << clk->div.high_shift); + val &= ~(GENMASK(clk->div.high_width - 1, 0) << clk->div.high_shift); + if (div_h) val |= div_h << clk->div.high_shift; - } else { - val &= ~(bit_mask(clk->div.high_width) - << clk->div.high_shift); - } - if (div_l) { - val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); + val &= ~(GENMASK(clk->div.low_width - 1, 0) << clk->div.low_shift); + if (div_l) val |= div_l << clk->div.low_shift; - } else { - val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); - } writel(val, asiu->div_base + clk->div.offset); return 0; diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c index 2dda4e8..6d467ed 100644 --- a/drivers/clk/bcm/clk-iproc-pll.c +++ b/drivers/clk/bcm/clk-iproc-pll.c @@ -154,7 +154,7 @@ static void __pll_disable(struct iproc_pll *pll) writel(val, pll->pwr_base + ctrl->aon.offset); /* power down the core */ - val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); + val &= ~(GENMASK(ctrl->aon.pwr_width - 1, 0) << ctrl->aon.pwr_shift); writel(val, pll->pwr_base + ctrl->aon.offset); } @@ -165,7 +165,7 @@ static int __pll_enable(struct iproc_pll *pll) /* power up the PLL and make sure it's not latched */ val = readl(pll->pwr_base + ctrl->aon.offset); - val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; + val |= GENMASK(ctrl->aon.pwr_width - 1, 0) << ctrl->aon.pwr_shift; val &= ~(1 << ctrl->aon.iso_shift); writel(val, pll->pwr_base + ctrl->aon.offset); @@ -200,9 +200,9 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; val = readl(pll->pll_base + reset->offset); - val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | - bit_mask(reset->kp_width) << reset->kp_shift | - bit_mask(reset->ka_width) << reset->ka_shift); + val &= ~(GENMASK(reset->ki_width - 1, 0) << reset->ki_shift | + GENMASK(reset->kp_width - 1, 0) << reset->kp_shift | + GENMASK(reset->ka_width - 1, 0) << reset->ka_shift); val |= ki << reset->ki_shift | kp << reset->kp_shift | ka << reset->ka_shift; val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; @@ -282,7 +282,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, /* program integer part of NDIV */ val = readl(pll->pll_base + ctrl->ndiv_int.offset); - val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); + val &= ~(GENAMSK(ctrl->ndiv_int.width - 1, 0) << ctrl->ndiv_int.shift); val |= vco->ndiv_int << ctrl->ndiv_int.shift; writel(val, pll->pll_base + ctrl->ndiv_int.offset); if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) @@ -291,7 +291,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, /* program fractional part of NDIV */ if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { val = readl(pll->pll_base + ctrl->ndiv_frac.offset); - val &= ~(bit_mask(ctrl->ndiv_frac.width) << + val &= ~(GENMASK(ctrl->ndiv_frac.width - 1, 0) << ctrl->ndiv_frac.shift); val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; writel(val, pll->pll_base + ctrl->ndiv_frac.offset); @@ -301,7 +301,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, /* program PDIV */ val = readl(pll->pll_base + ctrl->pdiv.offset); - val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); + val &= ~(GENMASK(ctrl->pdiv.width - 1, 0) << ctrl->pdiv.shift); val |= vco->pdiv << ctrl->pdiv.shift; writel(val, pll->pll_base + ctrl->pdiv.offset); if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) @@ -365,13 +365,13 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, */ val = readl(pll->pll_base + ctrl->ndiv_int.offset); ndiv_int = (val >> ctrl->ndiv_int.shift) & - bit_mask(ctrl->ndiv_int.width); + GENMASK(ctrl->ndiv_int.width - 1, 0); ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift; if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { val = readl(pll->pll_base + ctrl->ndiv_frac.offset); ndiv_frac = (val >> ctrl->ndiv_frac.shift) & - bit_mask(ctrl->ndiv_frac.width); + GENMASK(ctrl->ndiv_frac.width - 1, 0); if (ndiv_frac != 0) ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) | @@ -379,7 +379,7 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, } val = readl(pll->pll_base + ctrl->pdiv.offset); - pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); + pdiv = (val >> ctrl->pdiv.shift) & GENMASK(ctrl->pdiv.width - 1, 0); clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift; @@ -487,7 +487,7 @@ static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, return 0; val = readl(pll->pll_base + ctrl->mdiv.offset); - mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); + mdiv = (val >> ctrl->mdiv.shift) & GENMASK(ctrl->mdiv.width - 1, 0); if (mdiv == 0) mdiv = 256; @@ -534,12 +534,9 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; val = readl(pll->pll_base + ctrl->mdiv.offset); - if (div == 256) { - val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); - } else { - val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + val &= ~(GENMASK(ctrl->mdiv.width - 1, 0) << ctrl->mdiv.shift); + if (div < 256) val |= div << ctrl->mdiv.shift; - } writel(val, pll->pll_base + ctrl->mdiv.offset); if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) readl(pll->pll_base + ctrl->mdiv.offset); diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h index d834b7a..5e4b66f 100644 --- a/drivers/clk/bcm/clk-iproc.h +++ b/drivers/clk/bcm/clk-iproc.h @@ -24,7 +24,6 @@ #define IPROC_CLK_NAME_LEN 25 #define IPROC_CLK_INVALID_OFFSET 0xffffffff -#define bit_mask(width) ((1 << (width)) - 1) /* clocks that should not be disabled at runtime */ #define IPROC_CLK_AON BIT(0) diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c index deaa7f9..9397b54 100644 --- a/drivers/clk/bcm/clk-kona-setup.c +++ b/drivers/clk/bcm/clk-kona-setup.c @@ -307,7 +307,7 @@ static bool sel_valid(struct bcm_clk_sel *sel, const char *field_name, * in the array. */ max_sel = sel->parent_sel[sel->parent_count - 1]; - limit = (1 << sel->width) - 1; + limit = GENMASK(sel->width - 1, 0); if (max_sel > limit) { pr_err("%s: bad selector for %s " "(%u needs > %u bits)\n", diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c index d9c039c..f5aa1cc 100644 --- a/drivers/clk/bcm/clk-kona.c +++ b/drivers/clk/bcm/clk-kona.c @@ -30,22 +30,16 @@ /* Bitfield operations */ -/* Produces a mask of set bits covering a range of a 32-bit value */ -static inline u32 bitfield_mask(u32 shift, u32 width) -{ - return ((1 << width) - 1) << shift; -} - /* Extract the value of a bitfield found within a given register value */ static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) { - return (reg_val & bitfield_mask(shift, width)) >> shift; + return (reg_val >> shift) & GENMASK(width - 1, 0); } /* Replace the value of a bitfield found within a given register value */ static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) { - u32 mask = bitfield_mask(shift, width); + u32 mask = GENMASK(width - 1, 0) << shift; return (reg_val & ~mask) | (val << shift); } @@ -94,7 +88,7 @@ u64 scaled_div_max(struct bcm_clk_div *div) if (divider_is_fixed(div)) return (u64)div->u.fixed; - reg_div = ((u32)1 << div->u.s.width) - 1; + reg_div = GENMASK(div->u.s.width - 1, 0); return scaled_div_value(div, reg_div); } -- 2.1.4
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