Messages in this thread | | | Subject | Re: [alsa-devel] [PATCH v3] ASoC: Add support for NAU8825 codec to ASoC | From | Liam Girdwood <> | Date | Mon, 13 Jul 2015 10:23:10 +0100 |
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On Mon, 2015-07-13 at 15:33 +0800, Chih-Chiang Chang wrote: > +static void set_sys_clk(struct snd_soc_codec *codec, int sys_clk) > +{ > + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); > + > + pr_debug("%s :: sys_clk=%x\n", __func__, sys_clk); > + switch (sys_clk) { > + case NAU8825_INTERNALCLOCK: > + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, > + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_DIS); > + regmap_update_bits(nau8825->regmap, NAU8825_FLL_6, > + NAU8825_DCO_EN_MASK, NAU8825_DCO_EN); > + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, > + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_EN); > + break; > + case NAU8825_MCLK: > + default: > + regmap_update_bits(nau8825->regmap, NAU8825_FLL_6, > + NAU8825_DCO_EN_MASK, NAU8825_DCO_DIS); > + regmap_update_bits(nau8825->regmap, NAU8825_I2S_PCM_CTRL_2, > + NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE); > + /* FLL clock source from MCLK */ > + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, > + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_DIS); > + mdelay(2);
Probably best to sleep here rather than block, especially if this code will be used in init/PM sequences.
Btw, is there anyway to check whether the FLL actually achieves lock after the 2ms ?
> + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, > + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_EN); > + break; > + } > +} > +
Thanks
Liam
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