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    SubjectRe: [PATCH RFC] x86, tsc: Allow for high latency in quick_pit_calibrate()
    On 03/06/15 06:30, Andi Kleen wrote:
    >> Then the changelog should say that I think. The current text says
    >> "Fast TSC calibration will always fail", which, to me, suggests that
    >> either the slow calibration will work or that the changelog message
    >> should be changed.
    >
    > Ok. No, the slow calibration works I believe.

    Yeah, so the (only?) downside is the 50ms wasted on Fast TSC
    calibration. What about this?


    From: Adrian Hunter <adrian.hunter@intel.com>
    Date: Wed, 3 Jun 2015 10:39:46 +0300
    Subject: [PATCH] x86, tsc: Let high latency PIT fail fast in
    quick_pit_calibrate()

    If it takes longer than 12us to read the PIT counter lsb/msb,
    then the error margin will never fall below 500ppm within 50ms,
    and Fast TSC calibration will always fail.

    This patch detects when that will happen and fails fast. Note
    the failure message is not printed in that case because:
    1. it will always happen on that class of hardware
    2. the absence of the message is more informative than its
    presence

    Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
    ---
    arch/x86/kernel/tsc.c | 11 ++++++++++-
    1 file changed, 10 insertions(+), 1 deletion(-)

    diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
    index 7114c86af35e..673c4f25021f 100644
    --- a/arch/x86/kernel/tsc.c
    +++ b/arch/x86/kernel/tsc.c
    @@ -598,10 +598,19 @@ static unsigned long quick_pit_calibrate(void)
    if (!pit_expect_msb(0xff-i, &delta, &d2))
    break;

    + delta -= tsc;
    +
    + /*
    + * Extrapolate the error and fail fast if the error will
    + * never be below 500 ppm.
    + */
    + if (i == 1 &&
    + d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
    + return 0;
    +
    /*
    * Iterate until the error is less than 500 ppm
    */
    - delta -= tsc;
    if (d1+d2 >= delta >> 11)
    continue;

    --
    1.9.1



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