lkml.org 
[lkml]   [2015]   [Jun]   [10]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 3.12 083/111] drm/radeon: partially revert "fix VM_CONTEXT*_PAGE_TABLE_END_ADDR handling"
    Date
    From: Christian König <christian.koenig@amd.com>

    3.12-stable review patch. If anyone has any objections, please let me know.

    ===============

    commit 7c0411d2fabc2e2702c9871ffb603e251158b317 upstream.

    We have that bug for years and some users report side effects when fixing it on older hardware.

    So revert it for VM_CONTEXT0_PAGE_TABLE_END_ADDR, but keep it for VM 1-15.

    Signed-off-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Jiri Slaby <jslaby@suse.cz>
    ---
    drivers/gpu/drm/radeon/cik.c | 2 +-
    drivers/gpu/drm/radeon/evergreen.c | 2 +-
    drivers/gpu/drm/radeon/ni.c | 2 +-
    drivers/gpu/drm/radeon/r600.c | 2 +-
    drivers/gpu/drm/radeon/rv770.c | 2 +-
    drivers/gpu/drm/radeon/si.c | 2 +-
    6 files changed, 6 insertions(+), 6 deletions(-)

    diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
    index db86a9510b2c..944301337c58 100644
    --- a/drivers/gpu/drm/radeon/cik.c
    +++ b/drivers/gpu/drm/radeon/cik.c
    @@ -4557,7 +4557,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
    L2_CACHE_BIGK_FRAGMENT_SIZE(6));
    /* setup context0 */
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
    (u32)(rdev->dummy_page.addr >> 12));
    diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
    index 204e6a9adf3c..063b72fbfe1e 100644
    --- a/drivers/gpu/drm/radeon/evergreen.c
    +++ b/drivers/gpu/drm/radeon/evergreen.c
    @@ -2424,7 +2424,7 @@ static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
    WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
    WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
    diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
    index 5ef61a48056b..7dcf2ffddccf 100644
    --- a/drivers/gpu/drm/radeon/ni.c
    +++ b/drivers/gpu/drm/radeon/ni.c
    @@ -1241,7 +1241,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
    L2_CACHE_BIGK_FRAGMENT_SIZE(6));
    /* setup context0 */
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
    (u32)(rdev->dummy_page.addr >> 12));
    diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
    index 765833756909..2c0a0d7c2492 100644
    --- a/drivers/gpu/drm/radeon/r600.c
    +++ b/drivers/gpu/drm/radeon/r600.c
    @@ -942,7 +942,7 @@ static int r600_pcie_gart_enable(struct radeon_device *rdev)
    WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
    WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
    diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
    index 8cc9470df191..c4960ad71e5e 100644
    --- a/drivers/gpu/drm/radeon/rv770.c
    +++ b/drivers/gpu/drm/radeon/rv770.c
    @@ -916,7 +916,7 @@ static int rv770_pcie_gart_enable(struct radeon_device *rdev)
    WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
    WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
    diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
    index 455b9516bdd2..7dcd3c81f42a 100644
    --- a/drivers/gpu/drm/radeon/si.c
    +++ b/drivers/gpu/drm/radeon/si.c
    @@ -3961,7 +3961,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
    L2_CACHE_BIGK_FRAGMENT_SIZE(0));
    /* setup context0 */
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
    (u32)(rdev->dummy_page.addr >> 12));
    --
    2.4.2


    \
     
     \ /
      Last update: 2015-06-10 18:21    [W:4.171 / U:0.548 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site