[lkml]   [2015]   [Jun]   [1]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH v10 12/12] drivers/block/pmem: Map NVDIMM with ioremap_wt()
On Mon, Jun 1, 2015 at 1:58 AM, Ingo Molnar <> wrote:
> * Andy Lutomirski <> wrote:
>> You answered the wrong question. :) I understand the point of the non-temporal
>> stores -- I don't understand the point of using non-temporal stores to *WB
>> memory*. I think we should be okay with having the kernel mapping use WT
>> instead.
> WB memory is write-through, but they are still fully cached for reads.
> So non-temporal instructions influence how the CPU will allocate (or not allocate)
> WT cache lines.

I'm doing a terrible job of saying what I mean.

Given that we're using non-temporal writes, the kernel code should
work correctly and with similar performance regardless of whether the
mapping is WB or WT. It would still be correct, if slower, with WC or
UC, and, if we used explicit streaming reads, even that would matter

I think this means that we are free to switch the kernel mapping
between WB and WT as needed to improve DAX behavior. We could even
plausibly do it at runtime.


> Thanks,
> Ingo

Andy Lutomirski
AMA Capital Management, LLC

 \ /
  Last update: 2015-06-01 19:41    [W:0.084 / U:2.424 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site