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SubjectQuestion about barriers for ARM on tools/perf/
Hi Will,

I am working on moving the stuff we have for mb/rmb/wmb from
tools/perf/perf-sys.h to tools/include/asm/barrier.h, redirecting
to tools/arch/$ARCH/include/asm/barrier.h, to make it look like the
kernel and who knows, at some point even share the source code.

For now I am getting just what is needed for work on having
atomic.h done in the same fashion, to implement refcounts for various
perf data structures, starting with struct thread, for which I have
a patch that makes perf survive in high core count machines where it
currently crashes, most nobably 'perf top'.

While doing that I noticed that arm64 implementation, lastly
fixed in:

perf tools: Fix AAAAARGH64 memory barriers

By peterz, it implements those barriers as:

#define mb() asm volatile("dmb ish" ::: "memory")
#define wmb() asm volatile("dmb ishst" ::: "memory")
#define rmb() asm volatile("dmb ishld" ::: "memory")

Which are not the same as in the kernel, i.e. in
arch/arm64/include/asm/barrier.h, where the above are really smp_mb,
smp_wmb and smp_rmb.

Would it be enough for us to use the same implementation as the kernel?
I.e. make it be:

#define mb() asm volatile("dsb sy" ::: "memory")
#define wmb() asm volatile("dsb st" ::: "memory")
#define rmb() asm volatile("dsb ld" ::: "memory")

? If so I would then use those dsb/dmb macros, etc, to get tools/ to use
the proper instructions, etc.

I need now, for arm64, smp_mb, that is used by atomic_sub_return(), that
in turn is used by atomic_dec_and_test(), that I need for refcounts.

Can you clarify?

- Arnaldo

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