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SubjectRe: [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling
On Thu, May 07, 2015 at 03:56:25PM -0700, Andi Kleen wrote:
> +/* Same as HSW, plus TSC */
> +
> +struct pebs_record_v3 {

This is inconsistently named.

> + u64 flags, ip;
> + u64 ax, bx, cx, dx;
> + u64 si, di, bp, sp;
> + u64 r8, r9, r10, r11;
> + u64 r12, r13, r14, r15;
> + u64 status, dla, dse, lat;
> + u64 real_ip, tsx_tuning;
> + u64 tsc;
> +};
> @@ -958,6 +971,13 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
> data.txn = intel_hsw_transaction(pebs);
> }
>
> + /*
> + * v3 supplies an accurate time stamp, so we use that
> + * for the time stamp.
> + */
> + if (x86_pmu.intel_cap.pebs_format >= 3)
> + data.time = native_sched_clock_from_tsc(pebs->tsc);

That's wrong. It does not respect perf_event_attr::clock_id.




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