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SubjectRe: [PATCH v4 03/12] devicetree: Add bindings for the ATH79 DDR controllers
Hello.

On 5/31/2015 2:52 AM, Alban Bedel wrote:

> The DDR controller of the ARxxx and AR9xxx families provides an
> interface to flush the FIFO between various devices and the DDR.
> This is mainly used by the IRQ controller to flush the FIFO before
> running the interrupt handler of such devices.

> Signed-off-by: Alban Bedel <albeu@free.fr>
> ---
> v2: * Fix the node names to respect ePAPR
> v3: * Fix some typos
> * Really fix the node names this time
> ---
> .../memory-controllers/ath79-ddr-controller.txt | 35 ++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt

> diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
> new file mode 100644
> index 0000000..efe35a06
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
> @@ -0,0 +1,35 @@
> +Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
> +
> +The DDR controller of the ARxxx and AR9xxx families provides an interface

s/ARxxx/AR7xxx/.

> +to flush the FIFO between various devices and the DDR. This is mainly used
> +by the IRQ controller to flush the FIFO before running the interrupt handler
> +of such devices.
> +
> +Required properties:
> +
> +- compatible: has to be "qca,<soc-type>-ddr-controller",
> + "qca,[ar7100|ar7240]-ddr-controller" as fallback.
> + On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
> + fallback, otherwise "qca,ar7240-ddr-controller" should be used.
> +- reg: Base address and size of the controllers memory area

Controller's.

> +- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer
> + channel

Hm, index? The expectation for such props is the # of cells.

WBR, Sergei



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