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SubjectRe: [PATCH 4/6] edac, mce_amd_inj: Add capability to trigger apic interrupts
On 5/29/2015 10:36 AM, Borislav Petkov wrote:
> On Wed, May 27, 2015 at 02:03:36PM -0500, Aravind Gopalakrishnan wrote:
>>
>> +static void trigger_dfr_int(void *info)
>> +{
>> + asm volatile("int $244");
>> +}
>> +
>> +static void trigger_thr_int(void *info)
>> +{
>> + asm volatile("int $249");
>> +}
> Hardcoded naked numbers huh?
>
> Guess what happens when someone changes DEFERRED_ERROR_VECTOR and
> THRESHOLD_APIC_VECTOR.

Right. Sorry about that.
Fixed it thusly:
u8 dfr_vec = DEFERRED_ERROR_VECTOR;
asm volatile("int %0"
:: "n" (dfr_vec));

and similar for threshold interrupt as well.

Tested the above and it seems to work fine.

>
> - smp_call_function_single(cpu, trigger_mce, NULL, 0);
> + if (inj_type == DFR_INT_INJ)
> + smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
> + else if (inj_type == THR_INT_INJ)
> + smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
> + else
> + smp_call_function_single(cpu, trigger_mce, NULL, 0);
> I guess a switch-case is kinda offering itself here...
>

Ok, will switch it:)

Thanks,
-Aravind.


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