Messages in this thread | | | Date | Fri, 22 May 2015 11:35:05 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC |
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On 05/22/15 11:30, Brent Wang wrote: > Hello Stephen, > > 2015-05-22 13:20 GMT+08:00 Bintian <bintian.wang@huawei.com>: >> >>> >>> Is pl011 the uart device? Does it have a node in DT somewhere? If it >>> does, then we could put the assigned-parents properties in that node so >>> that when the pl011 probes the uart1 clock has its parent set to >>> clk_150m. See the "Assigned clock parents and rates" section of >>> Documentation/devicetree/bindings/clock/clock-bindings.txt. >>> >> I will verify this. > Currently the "assigned-clock*" doesn't work for pl011 UART device > node, maybe we will > do some fix for its driver later or other modules.
Why doesn't it work?
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