Messages in this thread | | | Date | Thu, 21 May 2015 11:00:53 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC |
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On 05/20/15 20:57, Bintian wrote: > >> >>> >>> + >>> +static void __init hi6220_clk_sys_init(struct device_node *np) >>> +{ >>> + struct hisi_clock_data *clk_data; >>> + >>> + clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS); >>> + if (!clk_data) >>> + return; >>> + >>> + hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, >>> + ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); >>> + >>> + hisi_clk_register_mux(hi6220_mux_clks_sys, >>> + ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); >>> + >>> + hi6220_clk_register_divider(hi6220_div_clks_sys, >>> + ARRAY_SIZE(hi6220_div_clks_sys), clk_data); >>> + >>> + if (!clk_data_ao) >>> + return; >>> + >>> + /* enable high speed clock on UART1 mux */ >>> + clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC], >>> + clk_data_ao->clk_data.clks[HI6220_150M]); >> >> Sorry I missed this one earlier. Can we do this clk_set_parent() through >> assigned-parents instead? > Uart1 has two clock parents in hi6220, and use "clk_tcxo" by default, > we use uart1 to connect BT in HiKey, and switch to "clk_150m" for high > speed mode of BT, but pl011 has no code to set clock rate or set clock > parents operation, so it's a easy way to do that here.
Is pl011 the uart device? Does it have a node in DT somewhere? If it does, then we could put the assigned-parents properties in that node so that when the pl011 probes the uart1 clock has its parent set to clk_150m. See the "Assigned clock parents and rates" section of Documentation/devicetree/bindings/clock/clock-bindings.txt.
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