Messages in this thread | | | Date | Fri, 15 May 2015 10:52:54 +0900 | From | Joonyoung Shim <> | Subject | Re: [PATCH 1/2] clk: divider: don't set_rate with CLK_DIVIDER_READ_ONLY flag |
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Hi Stephen,
On 05/13/2015 08:59 AM, Stephen Boyd wrote: > On 04/07, Joonyoung Shim wrote: >> Even if use CLK_DIVIDER_READ_ONLY flag, divider setting can be changed >> by set_rate callback. Don't change divider setting from set_rate >> callback of divider with CLK_DIVIDER_READ_ONLY flag. >> >> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> >> --- > > Is the rate actually changing? Or is it just a problem that we > may be writing the register to the same value it already is? >
If rate and parant_rate are different, it can write the register to different value. Even if the value is same but i think it's unnecessary to re-write the register.
Thanks.
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