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Subject[PATCH 4.0 09/72] MIPS: OCTEON: Use correct CSR to soft reset
Date
4.0-stable review patch.  If anyone has any objections, please let me know.

------------------


From: Chandrakala Chavva <cchavva@caviumnetworks.com>

Commit 9a49899eb88803dcc0ef437f09912f9a7b7a66fd upstream.

Also delete unused cvmx_reset_octeon()
This fixes reboot for Octeon III boards

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/9471/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/cavium-octeon/setup.c | 5 ++++-
arch/mips/include/asm/octeon/cvmx.h | 8 --------
2 files changed, 4 insertions(+), 9 deletions(-)

--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -413,7 +413,10 @@ static void octeon_restart(char *command

mb();
while (1)
- cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
+ if (OCTEON_IS_OCTEON3())
+ cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
+ else
+ cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
}


--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -436,14 +436,6 @@ static inline uint64_t cvmx_get_cycle_gl

/***************************************************************************/

-static inline void cvmx_reset_octeon(void)
-{
- union cvmx_ciu_soft_rst ciu_soft_rst;
- ciu_soft_rst.u64 = 0;
- ciu_soft_rst.s.soft_rst = 1;
- cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
-}
-
/* Return the number of cores available in the chip */
static inline uint32_t cvmx_octeon_num_cores(void)
{



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