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    Subject[PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
    Date
    A33 PIO has 7 ports which starts from PB and has two interrupt ports.

    Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
    ---
    .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
    drivers/pinctrl/sunxi/Kconfig | 5 +
    drivers/pinctrl/sunxi/Makefile | 1 +
    drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 +++++++++++++++++++++
    4 files changed, 521 insertions(+)
    create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c

    diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
    index fdd8046..9462ab7 100644
    --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
    +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
    @@ -16,6 +16,8 @@ Required properties:
    "allwinner,sun7i-a20-pinctrl"
    "allwinner,sun8i-a23-pinctrl"
    "allwinner,sun8i-a23-r-pinctrl"
    + "allwinner,sun8i-a33-pinctrl"
    +
    - reg: Should contain the register physical address and length for the
    pin controller.

    diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
    index 2eb893e..dd83aab 100644
    --- a/drivers/pinctrl/sunxi/Kconfig
    +++ b/drivers/pinctrl/sunxi/Kconfig
    @@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
    def_bool MACH_SUN8I
    select PINCTRL_SUNXI_COMMON

    +
    +config PINCTRL_SUN8I_A33
    + def_bool MACH_SUN8I
    + select PINCTRL_SUNXI_COMMON
    +
    config PINCTRL_SUN8I_A23_R
    def_bool MACH_SUN8I
    depends on RESET_CONTROLLER
    diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
    index b796d57..227a121 100644
    --- a/drivers/pinctrl/sunxi/Makefile
    +++ b/drivers/pinctrl/sunxi/Makefile
    @@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
    obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
    obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
    obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
    +obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
    obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
    diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
    new file mode 100644
    index 0000000..00265f0
    --- /dev/null
    +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
    @@ -0,0 +1,513 @@
    +/*
    + * Allwinner a33 SoCs pinctrl driver.
    + *
    + * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
    + *
    + * Based on pinctrl-sun8i-a23.c, which is:
    + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
    + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
    + *
    + * This file is licensed under the terms of the GNU General Public
    + * License version 2. This program is licensed "as is" without any
    + * warranty of any kind, whether express or implied.
    + */
    +
    +#include <linux/module.h>
    +#include <linux/platform_device.h>
    +#include <linux/of.h>
    +#include <linux/of_device.h>
    +#include <linux/pinctrl/pinctrl.h>
    +
    +#include "pinctrl-sunxi.h"
    +
    +static const struct sunxi_desc_pin sun8i_a33_pins[] = {
    + /* Hole */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
    + SUNXI_FUNCTION(0x3, "uart0"), /* TX */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
    + SUNXI_FUNCTION(0x3, "uart0"), /* RX */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
    + SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
    + SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
    + SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
    + SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
    + /* Hole */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
    + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
    + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
    + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
    + SUNXI_FUNCTION(0x3, "spi0")), /* CS */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* RE */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "nand"), /* DQS */
    + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
    + /* Hole */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
    + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
    + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
    + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
    + SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
    + SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
    + SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
    + SUNXI_FUNCTION(0x3, "uart1")), /* TX */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
    + SUNXI_FUNCTION(0x3, "uart1")), /* RX */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
    + SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
    + SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
    + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
    + /* Hole */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D2 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D3 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D4 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D5 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D6 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi")), /* D7 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi"), /* SCK */
    + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "csi"), /* SDA */
    + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out")),
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out")),
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out")),
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out")),
    + /* Hole */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
    + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
    + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
    + SUNXI_FUNCTION(0x3, "uart0")), /* TX */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
    + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
    + SUNXI_FUNCTION(0x3, "uart0")), /* RX */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
    + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
    + /* Hole */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart1"), /* TX */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart1"), /* RX */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
    + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
    + /* Hole */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "pwm0")),
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "pwm1")),
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "spi0"), /* CS */
    + SUNXI_FUNCTION(0x3, "uart3")), /* TX */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
    + SUNXI_FUNCTION(0x3, "uart3")), /* RX */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
    + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
    + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
    + SUNXI_FUNCTION(0x0, "gpio_in"),
    + SUNXI_FUNCTION(0x1, "gpio_out"),
    + SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
    + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
    +};
    +
    +static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
    + .pins = sun8i_a33_pins,
    + .npins = ARRAY_SIZE(sun8i_a33_pins),
    + .irq_banks = 2,
    +};
    +
    +static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
    +{
    + return sunxi_pinctrl_init(pdev,
    + &sun8i_a33_pinctrl_data);
    +}
    +
    +static const struct of_device_id sun8i_a33_pinctrl_match[] = {
    + { .compatible = "allwinner,sun8i-a33-pinctrl", },
    + {}
    +};
    +MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match);
    +
    +static struct platform_driver sun8i_a33_pinctrl_driver = {
    + .probe = sun8i_a33_pinctrl_probe,
    + .driver = {
    + .name = "sun8i-a33-pinctrl",
    + .of_match_table = sun8i_a33_pinctrl_match,
    + },
    +};
    +module_platform_driver(sun8i_a33_pinctrl_driver);
    +
    +MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
    +MODULE_DESCRIPTION("Allwinner a33 pinctrl driver");
    +MODULE_LICENSE("GPL");
    --
    1.9.1


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      Last update: 2015-05-10 09:01    [W:4.205 / U:0.064 seconds]
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