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    SubjectRe: [Linux-nvdimm] [PATCH 04/21] nd: create an 'nd_bus' from an 'nfit_desc'
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    On Wed, Apr 22, 2015 at 12:38 PM, Toshi Kani <toshi.kani@hp.com> wrote:
    > On Wed, 2015-04-22 at 12:28 -0700, Dan Williams wrote:
    >> On Wed, Apr 22, 2015 at 11:23 AM, Toshi Kani <toshi.kani@hp.com> wrote:
    >> > On Wed, 2015-04-22 at 11:20 -0700, Dan Williams wrote:
    >> >> On Wed, Apr 22, 2015 at 11:00 AM, Linda Knippers <linda.knippers@hp.com> wrote:
    >> >> Wait, point of clarification, DCRs (dimm-control-regions) have RFICs,
    >> >> not MEMDEVs (memory-device-to-spa-mapping). Toshi's original report
    >> >> was that an NFIT with a SPA+MEMDEV was failing to enable a PMEM
    >> >> device. That specific problem can be fixed by either deleting the
    >> >> MEMDEV, or adding a DCR.
    >> >
    >> > By a DCR, do you mean a DCR structure or SPA with Control Region GUID?
    >>
    >> Hmm, I meant a DCR as defined below. I agree you would not need a "SPA-DCR".
    >>
    >> > Adding a DCR structure does not solve this issue since it requires SPA
    >> > with Control Region GUID, which battery-backed DIMMs do not have.
    >>
    >> I would not go that far, half of a DCR entry is relevant for any
    >> NVDIMM, and half is only relevant if a DIMM offers BLK access:
    >>
    >> struct acpi_nfit_dcr {
    >> u16 type;
    >> u16 length;
    >> u16 dcr_index;
    >> u16 vendor_id;
    >> u16 device_id;
    >> u16 revision_id;
    >> u16 sub_vendor_id;
    >> u16 sub_device_id;
    >> u16 sub_revision_id;
    >> u8 reserved[6];
    >> u32 serial_number;
    >> u16 fic;
    >> <<<<< BLK relevant fields start here <<<<<
    >> u16 num_bcw;
    >> u64 bcw_size;
    >> u64 cmd_offset;
    >> u64 cmd_size;
    >> u64 status_offset;
    >> u64 status_size;
    >> u16 flags;
    >> u8 reserved2[6];
    >> };
    >
    > Yes, we do have a DCR entry. But we do not have a SPA-DCR.

    Got it. will fix.


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