Messages in this thread | | | Date | Mon, 20 Apr 2015 07:55:36 +0200 | From | leroy christophe <> | Subject | Re: [PATCH 00/11] powerpc8xx: Further optimisation of TLB handling |
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Le 20/04/2015 07:26, Christophe Leroy a écrit : > This patchset provides a further optimisation of TLB handling in the 8xx. > Main changes are based on: > - Using processor handling of PGD/PTE Validity bits instead of testing ourselves > the entries validity > - Aligning PGD address to allow direct bit manipulation > - Not saving registers like CR when not needed > > It also adds support to any TASK_SIZE > > Patchset: > 01 - powerpc/8xx: remove remaining unnecessary code in FixupDAR > 02 - powerpc/8xx: remove tests on PGDIR entry validity > 03 - powerpc32: Use kmem_cache memory for PGDIR > 04 - powerpc/8xx: Take benefit of aligned PGDIR > 05 - powerpc/8xx: Optimise access to swapper_pg_dir > 06 - powerpc/8xx: Remove duplicated code in set_context() > 07 - powerpc/8xx: macro for handling CPU15 errata > 08 - powerpc/8xx: Handle CR out of exception PROLOG/EPILOG > 09 - powerpc/8xx: dont save CR in SCRATCH registers > 10 - powerpc/8xx: Use SPRG2 instead of DAR for saving r3 > 11 - powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000 > > All changes have been successfully tested on MPC885 > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> Sorry, forget than one, my finger slipped and I resent a very old one already applied
Christophe
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