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SubjectRe: [PATCH 7/8] x86: Add documentation for rd/wr fs/gs base
On Fri, Apr 10, 2015 at 8:50 AM, Andi Kleen <andi@firstfloor.org> wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> v2: Minor updates to documentation requested in review.
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
> Documentation/x86/fsgs.txt | 76 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
> create mode 100644 Documentation/x86/fsgs.txt
>
> diff --git a/Documentation/x86/fsgs.txt b/Documentation/x86/fsgs.txt
> new file mode 100644
> index 0000000..26a1e29
> --- /dev/null
> +++ b/Documentation/x86/fsgs.txt
> @@ -0,0 +1,76 @@
> +
> +Using FS and GS prefixes on x86_64-linux
> +
> +The x86 architecture supports segment prefixes per instruction to add an
> +offset to an address. On 64bit x86, these are mostly nops, except for FS
> +and GS.
> +
> +This offers an efficient way to reference a global pointer.
> +
> +The compiler has to generate special code to use these base registers,
> +or they can be accessed with inline assembler.
> +
> + mov %gs:offset,%reg
> + mov %fs:offset,%reg
> +
> +FS is used to address the thread local segment (TLS), declared using
> +__thread. The compiler then automatically generates the correct prefixes and
> +relocations to access these values.
> +
> +FS is normally managed by the runtime code or the threading library.
> +
> +GS is freely available, but may need special (compiler or inline assembler)
> +code to use.
> +
> +Traditionally 64bit FS and GS could be set by the arch_prctl system call
> +
> + arch_prctl(ARCH_SET_GS, value)
> + arch_prctl(ARCH_SET_FS, value)
> +
> +[There was also an older method using modify_ldt(), inherited from 32bit,
> +but this is not discussed here.]
> +
> +However using a syscall is problematic for user space threading libraries
> +that want to context switch in user space. The whole point of them
> +is avoiding the overhead of a syscall. It's also cleaner for compilers
> +wanting to use the extra register to use instructions to write
> +it, or read it directly to compute addresses and offsets.
> +
> +Newer Intel CPUs (Ivy Bridge and later) added new instructions to directly
> +access these registers quickly from user context
> +
> + RDFSBASE %reg read the FS base (or _readfsbase_u64)
> + RDGSBASE %reg read the GS base (or _readgsbase_u64)
> +
> + WRFSBASE %reg write the FS base (or _writefsbase_u64)
> + WRGSBASE %reg write the GS base (or _writegsbase_u64)
> +
> +The instructions are supported by the CPU when the "fsgsbase" string is shown in
> +/proc/cpuinfo (or directly retrieved through the CPUID instruction).
> +The instructions are only available to 64bit binaries.
> +
> +However the kernel needs to explicitly enable these instructions, as it
> +may otherwise not correctly context switch the state. Newer Linux
> +kernels enable this. When the kernel did not enable the instruction
> +they will fault with an #UD exception.
> +
> +An FSGSBASE enabled kernel can be detected by checking the AT_HWCAP2
> +bitmask in the aux vector. When the HWCAP2_FSGSBASE bit is set the
> +kernel supports RDFSGSBASE.
> +
> + #include <sys/auxv.h>
> + #include <elf.h>
> +
> + /* Will be eventually in asm/hwcap.h */
> + #define HWCAP2_FSGSBASE (1 << 0)
> +
> + unsigned val = getauxval(AT_HWCAP2);
> + if (val & HWCAP2_FSGSBASE) {
> + asm("wrgsbase %0" :: "r" (ptr));
> + }
> +
> +Another requirement is that the FS or GS selector has to be zero
> +(is normally true unless changed explicitly)

IMO this is worthy of explanation.

I think that your __switch_to is buggy and that's why the selectors
need to be zero. Is that the only issue? If so, let's fix the bug
instead.

--Andy


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