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    Subject[PATCH 3.12 098/175] drm/radeon: workaround for CP HW bug on CIK
    Date
    From: Christian König <christian.koenig@amd.com>

    3.12-stable review patch. If anyone has any objections, please let me know.

    ===============

    commit a9c73a0e022c33954835e66fec3cd744af90ec98 upstream.

    Emit the EOP twice to avoid cache flushing problems.

    Signed-off-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Jiri Slaby <jslaby@suse.cz>
    ---
    drivers/gpu/drm/radeon/cik.c | 16 +++++++++++++++-
    1 file changed, 15 insertions(+), 1 deletion(-)

    diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
    index 76bf1f29d7cb..6e2e4a859047 100644
    --- a/drivers/gpu/drm/radeon/cik.c
    +++ b/drivers/gpu/drm/radeon/cik.c
    @@ -3027,7 +3027,21 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
    struct radeon_ring *ring = &rdev->ring[fence->ring];
    u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

    - /* EVENT_WRITE_EOP - flush caches, send int */
    + /* Workaround for cache flush problems. First send a dummy EOP
    + * event down the pipe with seq one below.
    + */
    + radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
    + radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
    + EOP_TC_ACTION_EN |
    + EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
    + EVENT_INDEX(5)));
    + radeon_ring_write(ring, addr & 0xfffffffc);
    + radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
    + DATA_SEL(1) | INT_SEL(0));
    + radeon_ring_write(ring, fence->seq - 1);
    + radeon_ring_write(ring, 0);
    +
    + /* Then send the real EOP event down the pipe. */
    radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
    radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
    EOP_TC_ACTION_EN |
    --
    2.3.0


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