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    SubjectRe: [PATCH 3/7] x86/intel_rdt: Support cache bit mask for Intel CAT
    Hello, Vikas.

    On Fri, Feb 27, 2015 at 11:34:16AM -0800, Vikas Shivappa wrote:
    > This cgroup subsystem would basically let the user partition one of the
    > Platform shared resource , the LLC cache. This could be extended in future

    I suppose LLC means last level cache? It'd be great if you can spell
    out the full term when the abbreviation is first referenced in the
    comments or documentation.

    > to partition more shared resources when there is hardware support that way
    > we may eventually have more files in the cgroup. RDT is a generic term for
    > platform resource sharing.

    > For more information you can refer to section 17.15 of Intel SDM.
    > We did go through quite a bit of discussion on lkml regarding adding the
    > cgroup interface for CAT and the patches were posted only after that.
    > This cgroup would not interact with other cgroups in the sense would not
    > modify or add any elements to existing cgroups - there was such a proposal
    > but was removed as we did not get agreement on lkml.
    >
    > the original lkml thread is here from 10/2014 for your reference -
    > https://lkml.org/lkml/2014/10/16/568

    Yeap, I followed that thread and this being a separate controller
    definitely makes a lot more sense.

    > I
    > >take it that the feature implemented is too coarse to allow for weight
    > >based distribution?
    > >
    > Could you please clarify more on this ? However there is a limitation from
    > hardware that there have to be a minimum of 2 bits in the cbm if thats what
    > you referred to. Otherwise the bits in the cbm directly map to the number of
    > cache ways and hence the cache capacity ..

    Right, so the granularity is fairly coarse and specifying things like
    "distribute cache in 4:2:1 (or even in absolute bytes) to these three
    cgroups" wouldn't work at all.

    Thanks.

    --
    tejun


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