Messages in this thread Patch in this message | | | From | Andi Kleen <> | Subject | [PATCH 1/3] perf, x86: Reset more state in PMU reset | Date | Fri, 27 Feb 2015 09:48:30 -0800 |
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From: Andi Kleen <ak@linux.intel.com>
The PMU reset code didn't quite keep up with newer PMU features. Improve it a bit to really reset a modern PMU:
- Clear all overflow status - Clear LBRs and freezing state - Disable fixed counters too
Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 3c024ba..0a48094 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1596,6 +1596,17 @@ static void intel_pmu_reset(void) if (ds) ds->bts_index = ds->bts_buffer_base; + /* Ack all overflows and disable fixed counters */ + if (x86_pmu.version >= 2) { + intel_pmu_ack_status(intel_pmu_get_status()); + wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); + } + + /* Reset LBRs and LBR freezing */ + if (x86_pmu.lbr_nr) + update_debugctlmsr(get_debugctlmsr() & + ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); + local_irq_restore(flags); } -- 1.9.3
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