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Subject[RESEND PATCH 1/2] arm: socfpga: update l2 cache settings
Date
From: Dinh Nguyen <dinguyen@opensource.altera.com>

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/mach-socfpga/socfpga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 383d61e..a5f1fda 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -104,7 +104,8 @@ static const char *altera_dt_match[] = {
};

DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
- .l2c_aux_val = 0,
+ .l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
+ L310_AUX_CTRL_INSTR_PREFETCH,
.l2c_aux_mask = ~0,
.smp = smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
--
2.2.1


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