Messages in this thread | | | Date | Thu, 17 Dec 2015 16:45:55 +0800 | From | Herbert Xu <> | Subject | Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value |
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On Sun, Dec 13, 2015 at 03:30:41AM -0800, Haren Myneni wrote: > > NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is > nothing to do with NX request. Since this bit can be set with other > valuable return status, mast this bit. > > One of other bits (INITIATED, BUSY or REJECTED) will be returned for > any given NX request. > > Signed-off-by: Haren Myneni <haren@us.ibm.com>
Patch applied. Thanks. -- Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
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