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SubjectRe: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access
On Thursday 10 December 2015 14:14:11, Bhuvanchandra DV wrote:
> On 12/10/2015 12:45 PM, Alexander Stein wrote:
> > On Thursday 10 December 2015 11:25:30, Bhuvanchandra DV wrote:
> >> DSPI instances in Vybrid have a different amount of chip selects
> >> and CTARs (Clock and transfer Attributes Register). In case of
> >> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
> >> implementation CTAR offset is derived from CS instance which will
> >> lead to out of bound access if chip select instance is greater than
> >> CTAR register instance, hence use single CTAR0 register for all CS
> >> instances. Since we write the CTAR register anyway before each access,
> >> there is no value in using the additional CTAR registers. Also one
> >> should not program a value in CTAS for a CTAR register that is not
> >> present, hence configure CTAS to use CTAR0.
> >
> > Shouldn't the information put into struct fsl_dspi_devtype_data how much CTAR and CS the actual implementation has available? E.g. LS1021A has 6 CS and 4 CTAR
> I guess still this will not help us when CS instance greater than CTAR
> instance is selected. Other point to consider here is we are writing the
> CTAR register before every access, so for us there is no additional
> advantage of using multiple CTAR registers.

Please have a look at 5cc7b04740effa5cc0af53f434134b5859d58b73 which addresses this problem for the 4 CTAR and 6 CS case.
I'm unsure how multiple CTAR will help at all. But at the end the amount of CS seems to be different for different implementations. So this still needs to be added to fsl_dspi_devtype_data.

Best regards,
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