Messages in this thread | | | Date | Sat, 7 Nov 2015 00:12:25 -0800 | Subject | Re: [PATCH 0/2] "big hammer" for DAX msync/fsync correctness | From | Dan Williams <> |
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On Fri, Nov 6, 2015 at 10:50 PM, Thomas Gleixner <tglx@linutronix.de> wrote: > On Fri, 6 Nov 2015, H. Peter Anvin wrote: >> On 11/06/15 15:17, Dan Williams wrote: >> >> >> >> Is it really required to do that on all cpus? >> > >> > I believe it is, but I'll double check. >> > >> >> It's required on all CPUs on which the DAX memory may have been dirtied. >> This is similar to the way we flush TLBs. > > Right. And that's exactly the problem: "may have been dirtied" > > If DAX is used on 50% of the CPUs and the other 50% are plumming away > happily in user space or run low latency RT tasks w/o ever touching > it, then having an unconditional flush on ALL CPUs is just wrong > because you penalize the uninvolved cores with a completely pointless > SMP function call and drain their caches. >
It's not wrong and pointless, it's all we have available outside of having the kernel remember every virtual address that might have been touched since the last fsync and sit in a loop flushing those virtual address cache line by cache line.
There is a crossover point where wbinvd is better than a clwb loop that needs to be determined.
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