[lkml]   [2015]   [Nov]   [3]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [GIT PULL] parisc architecture updates for v4.3
On Tue, Nov 3, 2015 at 3:03 PM, Helge Deller <> wrote:
> Sadly it's nowhere clearly documented how big the L1 cacheline of parisc really is.


Particularly that "it might actually be 16 bytes" from the thread
according to John David Anglin. I didn't expect anybody to really have
that small a line size any more.

> I was not very much concerned about any over-alignment, but about the
> performance. Reducing L1_CACHE_BYTES gave a performance improvement
> on parisc, most likely since we protect atomic accesses through our
> atomic spinlocks anyway.

Well, we do end up using L1_CACHE_BYTES to avoid false sharing in some
places, where it's not so much about atomic accesses, as just trying
to avoid having different CPU's step on each other when not needed. So
it's not necessarily about atomic accesses per se.

But if it's actually possible that the pa-risc L1 line size is really
just 16 bytes, I guess that objection to the patch goes away. My
automatic reaction was "that's not real, it's some odd workaround",
but if it is actually real...


 \ /
  Last update: 2015-11-04 00:41    [W:0.069 / U:0.512 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site