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SubjectRe: [PATCH] clk: qcom: Specify LE device endianness
Stephen Boyd <> writes:

> All these clock controllers are little endian devices, but so far
> we've been relying on the regmap mmio bus handling this for us
> without explicitly stating that fact. After commit 4a98da2164cf
> (regmap-mmio: Use native endianness for read/write, 2015-10-29),
> the regmap mmio bus will read/write with the __raw_*() IO
> accessors, instead of using the readl/writel() APIs that do
> proper byte swapping for little endian devices.
> So if we're running on a big endian processor and haven't
> specified the endianness explicitly in the regmap config or in
> DT, we're going to switch from doing little endian byte swapping
> to big endian accesses without byte swapping, leading to some
> confusing results. On my apq8074 dragonboard, this causes the
> device to fail to boot as we access the clock controller with
> big endian IO accesses even though the device is little endian.
> Specify the endianness explicitly so that the regmap core
> properly byte swaps the accesses for us.
> Reported-by: Kevin Hilman <>
> Cc: Simon Arlott <>
> Cc: Mark Brown <>
> Signed-off-by: Stephen Boyd <>

Tested-by: Kevin Hilman <>

Verified that this patch on top of next-20151118 gets my 2 8x94 boards
booting again with big-endian kernel.


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