lkml.org 
[lkml]   [2015]   [Nov]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH] brcmnand: Clear EXT_ADDR error registers in PIO mode
From
Date
On 17/11/15 00:40, Brian Norris wrote:
> + bcm-kernel-feedback-list
>
> On Mon, Nov 16, 2015 at 10:05:39PM +0000, Simon Arlott wrote:
>> If an error occurs in flash above 4GB in PIO mode then the EXT_ADDR
>> registers will be set to the location of the error and never cleared.
>>
>> Reset them to 0 before reading.
>>
>> Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
>
> Patch looks OK. Did you see this problem in practice, or is this just
> theoretical? I thought the documentation seemed to suggest these
> registers were cleared together with their non-_EXT counterparts. But
> implementation definitely trumps documentation for HW.

It's theoretical (I don't have 4GB+ flash), but the Broadcom version of
the NAND driver does this.

> Brian
>
>> ---
>> drivers/mtd/nand/brcmnand/brcmnand.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c b/drivers/mtd/nand/brcmnand/brcmnand.c
>> index 12c6190..2c8f67f 100644
>> --- a/drivers/mtd/nand/brcmnand/brcmnand.c
>> +++ b/drivers/mtd/nand/brcmnand/brcmnand.c
>> @@ -1400,6 +1400,8 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
>> /* Clear error addresses */
>> brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
>> brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
>> + brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
>> + brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
>>
>> brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
>> (host->cs << 16) | ((addr >> 32) & 0xffff));
>> --
>> 2.1.4
>>
>> --
>> Simon Arlott
>


--
Simon Arlott


\
 
 \ /
  Last update: 2015-11-17 09:01    [W:0.099 / U:0.132 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site