Messages in this thread | | | From | Dmitry Malkin <> | Subject | Re: [PATCH v3 04/12] usb: xhci: dbc: add support for Intel xHCI dbc quirk | Date | Tue, 17 Nov 2015 10:28:59 +0000 |
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On Mon, 16 Nov 2015 10:18:42 +0800, Lu Baolu wrote: > This quirk works as well if debug host doesn't have DBC. I didn't try a > DBC-capable debug host yet.
Hi,
I went through it again, with your v3 patch series on top of vanilla v4.3.0.
Two targets, one host, all with Intel chipset (XHCI device 0:14.0 with VID:8086). Targets DIDs are 9c31 (8-series chipset) and 9d2f (100-series chipset). Host DID is 8c31 (8-series).
I can only further confirm my previous observations. The host cannot see the target (there is no debug device) at all, until I manually re-plug a debug cable. Cable plugged in, prior to starting the target.
I think that trying a Hot Reset for all disconnected USB 3.0 ports on the debug target *just before* setting DCE bit is inherently racy.
What if the number of disconnected ports changes or if someone will insert a print statement or refactors your code?
Also sending TS2 to the debug host port will either: - get dropped by its hub as unsupported upstream request, or - get ignored due to SS.Inactive port state
Could you explain what exactly you workaround does at the low level?
-- with best regards, Dmitry Malkin
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