lkml.org 
[lkml]   [2015]   [Nov]   [10]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP
From
Date
Hi Rob,

On 11/7/2015 11:33 PM, Rob Herring wrote:
> On Fri, Nov 6, 2015 at 3:11 PM, Kapil Hali <kapilh@broadcom.com> wrote:
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>> ---
>> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36 ++++++++++++++++++++++
>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>> 2 files changed, 37 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> + - enable-method = "brcm,bcm-nsp-smp";
>
> As I said already, this is supposed to be per cpu.
>
>> + - secondary-boot-reg = <...>;
>
> And then you might as well move this too.
>
NS/NSP family of SoCs have maximum of two cores. There would not be a
need for another boot-reg in this family of SoCs. However, I agree, it
should go to individual CPU nodes. I will do the change in the next patch.
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register used to request the ROM holding pen
>> +code release a secondary CPU.
>> +
>> +Example:
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + enable-method = "brcm,bcm-nsp-smp";
>> + secondary-boot-reg = <0xffff042c>;
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + next-level-cache = <&L2>;
>> + reg = <0>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + next-level-cache = <&L2>;
>> + reg = <1>;
>> + };
>> + };
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 91e6e5c..6abe3f3 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>> "allwinner,sun8i-a23"
>> "arm,psci"
>> "brcm,brahma-b15"
>> + "brcm,bcm-nsp-smp"
>> "marvell,armada-375-smp"
>> "marvell,armada-380-smp"
>> "marvell,armada-390-smp"
>> --
>> 2.1.0
>>
Thanks,
Kapil Hali


\
 
 \ /
  Last update: 2015-11-10 17:41    [W:0.161 / U:0.496 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site