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SubjectRe: [PATCH 2/2] x86/cpufeature: Add CLZERO feature
On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote:
> CLZERO instruction introduced in AMD Fam17h processors
> zero's out a 64 byte cache line specified in RAX.
>
> Add the bit here to allow /proc/cpuinfo to list the feature
>
> Signed-off-by: Wan Zongshun <Vincent.Wan@amd.com>
> Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>

This SOB chain looks wrong - if Vincent is the author and you're only
sending the patch, then his "From:" needs to appear before the commit
message. git send-email does that correctly, provided the authorship is
correctly set in the local branch you're sending the patch from.

> ---
> arch/x86/include/asm/cpufeature.h | 5 ++++-
> arch/x86/kernel/cpu/common.c | 1 +
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 9727b3b..82d7c25 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -12,7 +12,7 @@
> #include <asm/disabled-features.h>
> #endif
>
> -#define NCAPINTS 13 /* N 32-bit words worth of info */
> +#define NCAPINTS 14 /* N 32-bit words worth of info */
> #define NBUGINTS 1 /* N 32-bit bug flags */
>
> /*
> @@ -255,6 +255,9 @@
> /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
> #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
>
> +/* AMD extended feature extension, CPUID level 0x80000008 (ebx), word 13 */

extended ... extension sounds like a tautology, please sanitize.

> +#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */

...

--
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
--


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