Messages in this thread | | | Date | Tue, 20 Oct 2015 10:37:21 +0200 | From | Ingo Molnar <> | Subject | Re: Q: schedule() and implied barriers on arm64 |
| |
* Peter Zijlstra <peterz@infradead.org> wrote:
> On Mon, Oct 19, 2015 at 04:21:08PM +0100, Catalin Marinas wrote: > > On Mon, Oct 19, 2015 at 09:06:05AM +0200, Ingo Molnar wrote: > > > * Peter Zijlstra <peterz@infradead.org> wrote: > > > > > > > In any case, its all moot now, since Paul no longer requires schedule() to imply > > > > a full barrier. > > > > > > > > [...] > > > > > > Nevertheless from a least-surprise POV it might be worth guaranteeing it, > > > because I bet there's tons of code that assumes that schedule() is a heavy > > > operation and it's such an easy mistake to make. Since we are so close to > > > having that guarantee, we might as well codify it? > > > > FWIW, the arm64 __switch_to() has a heavy barrier (DSB) but the reason for > > this was to cope with potentially interrupted cache or TLB maintenance (which > > require a DSB on the same CPU) and thread migration to another CPU. > > Right, but there's a path through schedule() that does not pass through > __switch_to(); when we pick the current task as the most eligible task and next > == prev. > > In that case there really only is the wmb, a spin lock, an atomic op and a spin > unlock (and a whole bunch of 'normal' code of course).
Yeah, so my concern is that this is a rare race that might be 'surprising' for developers relying on various schedule() constructs. Especially as it's a full barrier on x86 (the most prominent SMP platform at the moment) there's a real danger of hard to debug bugs creeping to other architectures.
So I think we should just do the small step of making it a full barrier everywhere - it's very close to it in any case, and it shouldn't really matter for performance. Agreed?
Thanks,
Ingo
| |