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    Subject[PATCH v12 8/9] ARM: EXYNOS: Add support for non-secure L2X0 resume
    Date
    From: Tomasz Figa <t.figa@samsung.com>

    On Exynos SoCs it is necessary to resume operation of L2C early in
    assembly code, because otherwise certain systems will crash. This patch
    adds necessary code to non-secure resume handler.

    Signed-off-by: Tomasz Figa <t.figa@samsung.com>
    [rewrote the code accessing l2x0_saved_regs]
    Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
    Acked-by: Arnd Bergmann <arnd@arndb.de>
    Acked-by: Kukjin Kim <kgene.kim@samsung.com>
    ---
    arch/arm/mach-exynos/sleep.S | 46 ++++++++++++++++++++++++++++++++++++++++++++
    1 file changed, 46 insertions(+)

    diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
    index e3c373082bbe..31d25834b9c4 100644
    --- a/arch/arm/mach-exynos/sleep.S
    +++ b/arch/arm/mach-exynos/sleep.S
    @@ -16,6 +16,8 @@
    */

    #include <linux/linkage.h>
    +#include <asm/asm-offsets.h>
    +#include <asm/hardware/cache-l2x0.h>
    #include "smc.h"

    #define CPU_MASK 0xff0ffff0
    @@ -74,6 +76,45 @@ ENTRY(exynos_cpu_resume_ns)
    mov r0, #SMC_CMD_C15RESUME
    dsb
    smc #0
    +#ifdef CONFIG_CACHE_L2X0
    + adr r0, 1f
    + ldr r2, [r0]
    + add r0, r2, r0
    +
    + /* Check that the address has been initialised. */
    + ldr r1, [r0, #L2X0_R_PHY_BASE]
    + teq r1, #0
    + beq skip_l2x0
    +
    + /* Check if controller has been enabled. */
    + ldr r2, [r1, #L2X0_CTRL]
    + tst r2, #0x1
    + bne skip_l2x0
    +
    + ldr r1, [r0, #L2X0_R_TAG_LATENCY]
    + ldr r2, [r0, #L2X0_R_DATA_LATENCY]
    + ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
    + mov r0, #SMC_CMD_L2X0SETUP1
    + smc #0
    +
    + /* Reload saved regs pointer because smc corrupts registers. */
    + adr r0, 1f
    + ldr r2, [r0]
    + add r0, r2, r0
    +
    + ldr r1, [r0, #L2X0_R_PWR_CTRL]
    + ldr r2, [r0, #L2X0_R_AUX_CTRL]
    + mov r0, #SMC_CMD_L2X0SETUP2
    + smc #0
    +
    + mov r0, #SMC_CMD_L2X0INVALL
    + smc #0
    +
    + mov r1, #1
    + mov r0, #SMC_CMD_L2X0CTRL
    + smc #0
    +skip_l2x0:
    +#endif /* CONFIG_CACHE_L2X0 */
    skip_cp15:
    b cpu_resume
    ENDPROC(exynos_cpu_resume_ns)
    @@ -83,3 +124,8 @@ cp15_save_diag:
    .globl cp15_save_power
    cp15_save_power:
    .long 0 @ cp15 power control
    +
    +#ifdef CONFIG_CACHE_L2X0
    + .align
    +1: .long l2x0_saved_regs - .
    +#endif /* CONFIG_CACHE_L2X0 */
    --
    1.9.2


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