lkml.org 
[lkml]   [2015]   [Jan]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 2/9] MIPS: Read CPU IRQ line that FDC to routed to
    Date
    Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC)
    interrupt from the IntCtl register and store it in cp0_fdc_irq where
    platform implementations of the new weak platform function
    get_c0_fdc_int() can refer to it.

    Signed-off-by: James Hogan <james.hogan@imgtec.com>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    ---
    arch/mips/include/asm/irq.h | 3 +++
    arch/mips/kernel/traps.c | 11 +++++++++++
    2 files changed, 14 insertions(+)

    diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
    index 5a4e1bb8fb1b..f0db99f8defe 100644
    --- a/arch/mips/include/asm/irq.h
    +++ b/arch/mips/include/asm/irq.h
    @@ -47,6 +47,9 @@ extern void free_irqno(unsigned int irq);
    extern int cp0_compare_irq;
    extern int cp0_compare_irq_shift;
    extern int cp0_perfcount_irq;
    +extern int cp0_fdc_irq;
    +
    +extern int __weak get_c0_fdc_int(void);

    void arch_trigger_all_cpu_backtrace(bool);
    #define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
    diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
    index 9c109fd8ba99..290da81c0532 100644
    --- a/arch/mips/kernel/traps.c
    +++ b/arch/mips/kernel/traps.c
    @@ -1920,6 +1920,12 @@ int cp0_compare_irq_shift;
    int cp0_perfcount_irq;
    EXPORT_SYMBOL_GPL(cp0_perfcount_irq);

    +/*
    + * Fast debug channel IRQ or -1 if not present
    + */
    +int cp0_fdc_irq;
    +EXPORT_SYMBOL_GPL(cp0_fdc_irq);
    +
    static int noulri;

    static int __init ulri_disable(char *s)
    @@ -2001,15 +2007,20 @@ void per_cpu_trap_init(bool is_boot_cpu)
    *
    * o read IntCtl.IPTI to determine the timer interrupt
    * o read IntCtl.IPPCI to determine the performance counter interrupt
    + * o read IntCtl.IPFDC to determine the fast debug channel interrupt
    */
    if (cpu_has_mips_r2) {
    cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
    cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
    cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
    + cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
    + if (!cp0_fdc_irq)
    + cp0_fdc_irq = -1;
    } else {
    cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
    cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
    cp0_perfcount_irq = -1;
    + cp0_fdc_irq = -1;
    }

    if (!cpu_data[cpu].asid_cache)
    --
    2.0.5


    \
     
     \ /
      Last update: 2015-01-29 12:21    [W:4.288 / U:0.228 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site