Messages in this thread | | | From | Wincy Van <> | Date | Wed, 21 Jan 2015 18:35:12 +0800 | Subject | Re: [PATCH v2 5/5] KVM: nVMX: Enable nested posted interrupt processing. |
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On Wed, Jan 21, 2015 at 4:49 PM, Zhang, Yang Z <yang.z.zhang@intel.com> wrote: >>>> + if (vector == vmcs12->posted_intr_nv && + >>>> nested_cpu_has_posted_intr(vmcs12)) { + if (vcpu->mode >>>> == IN_GUEST_MODE) + apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), + >>>> POSTED_INTR_VECTOR); + else { >>>> + r = -1; + goto out; + >>>> } + + /* + * if posted intr is >>>> done by hardware, the + * corresponding eoi was sent to >>>> L0. Thus + * we should send eoi to L1 manually. + >>>> */ + kvm_apic_set_eoi_accelerated(vcpu, + >>>> vmcs12->posted_intr_nv); >>> >>> Why this is necessary? As your comments mentioned, it is done by >>> hardware not L1, why L1 should aware of it? >>> >> >> According to SDM 29.6, if the processor recognizes a posted interrupt, >> it will send an EOI to LAPIC. >> If the posted intr is done by hardware, the processor will send eoi to >> hardware LAPIC, not L1's, just like the none-nested case(the physical >> interrupt is dismissed). So we should take care of the L1's LAPIC and send an eoi to it. > > No. You are not emulating the PI feature. You just reuse the hardware's capability. So you don't need to let L1 know it. >
Agreed, I had thought we have already set L1's IRR before this, I was wrong.
BTW, I was trying to complete the nested posted intr manually if the dest vcpu is in_guest_mode but not IN_GUEST_MODE, but I found that it is difficult to set RVI of the destination vcpu timely, because we should keep the RVI, PIR and ON in sync : (
I think it is better to do a nested vmexit in the case above, rather than emulate it, because that case is much less than the hardware case.
Thanks,
Wincy.
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