Messages in this thread | | | Date | Mon, 08 Sep 2014 19:30:29 -0700 | From | "H. Peter Anvin" <> | Subject | Re: bit fields && data tearing |
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On 09/08/2014 03:39 PM, James Bottomley wrote: > > I don't understand what you mean by "pass each other". Atomicity > guarantees are not ordering guarantees in a SMP environment. The > guarantee is that if you follow the rules when two CPUs update the same > natural width aligned object simultaneously using the same primitive, > the result is either one or the other of their updates. Which one wins > (the ordering) isn't defined. >
I'm trying to figure out why it would possibly make a difference in any kind of sane system if gcc fuses accesses.
Assuming bigendian for the moment, I would expect that if CPU 1 does a write of 0x01020304 to address 0 and CPU 2 does a write of 0x0506 to address 2, that the end result would be either 0x01020304 or 0x01020506. Similarly, I would expect that if these operations are both done on the same CPU in that order, that the result would unambiguously be 0x01020506.
I would strongly suspect an architecture which does not provide those guarantees is an outlier.
-hpa
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