Messages in this thread | | | Date | Mon, 08 Sep 2014 19:36:00 -0400 | From | Waiman Long <> | Subject | Re: Question reg. asm/qrwlock.h |
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On 09/05/2014 07:45 PM, Pranith Kumar wrote: > Hi Waiman, > > I see that in arch/x86/include/asm/qrwlock.h, there is this snippet within > > #ifndef CONFIG_X86_PPRO_FENCE > #define queue_write_unlock queue_write_unlock > static inline void queue_write_unlock(struct qrwlock *lock) > { > barrier(); > ACCESS_ONCE(*(u8 *)&lock->cnts) = 0; > } > #endif > > > I've been trying to understand why this special case is necessary for > PPRO. Could you please explain? > > Thanks!
This is related to the memory ordering of the x86 architecture. Modern x86 processor has pretty strong memory ordering semantics where only stores can be reordered after load. So a barrier() call is a good enough memory barrier except for some older x86 processors (Pentium Pro) that should have CONFIG_X86_PPRO_FENCE set. In that case, atomic instruction like cmpxchg() will be needed to ensure proper memory ordering.
-Longman
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