Messages in this thread | | | Date | Mon, 29 Sep 2014 11:36:57 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH V5 02/16] perf, core: introduce pmu context switch callback |
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On Sat, Sep 27, 2014 at 06:47:41PM +0200, Frederic Weisbecker wrote:
Trim replies already -- I should really go write that auto-bounce for excessive quoting already.
> I wonder if it's worth to create such an arch callback and core corner case. > How about just scheduling out then in the events that have lbr, wouldn't we > have more simple code in the end?
That depends a bit, the lbr save/restore is indeed very expensive (at least 16 msr reads and 16 msr writes -- when assuming 16 deep lbr), but this is still on about the same order of msr writes required to switch 4 counters (esp. if we include the PEBS msrs).
So at that point we still win about half the context switch cost by not doing an unconditional sched out / sched in.
Also, there are more consumers of this thing.
> Besides, BTS would benefit from that too. I can't seem to find where it is > flushed when a task context switches inside a same perf context. It seems > that it doesn't happen, BTS traces are flushed only on event stop (and overflow IRQ) > and events aren't stopped if a context switch happens in the same perf context. > Having Y task bts traces from task X event is probably not what we want.
Flushing the BTS is indeed a good point, but that would definitely benefit from this, draining the BTS buffer is likely faster than doing all those MSR writes.
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