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Subject[PATCH V2 11/24] MIPS: Malta: Move MSC01 interrupt base
Date
The GIC on Malta boards supports a total of 47 interrupts (40 shared
and 7 local) and is assigned a base of 24. This overlaps with the
MSC01 interrupt assignments which have a base of 64, so move the MSC01
interrupt base back a bit to give the GIC some room.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
---
No changes from v1.
---
arch/mips/include/asm/mips-boards/maltaint.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index e330732..4186606 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -33,18 +33,18 @@
#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4

/*
- * Interrupts 64..127 are used for Soc-it Classic interrupts
+ * Interrupts 96..127 are used for Soc-it Classic interrupts
*/
-#define MSC01C_INT_BASE 64
+#define MSC01C_INT_BASE 96

/* SOC-it Classic interrupt offsets */
#define MSC01C_INT_TMR 0
#define MSC01C_INT_PCI 1

/*
- * Interrupts 64..127 are used for Soc-it EIC interrupts
+ * Interrupts 96..127 are used for Soc-it EIC interrupts
*/
-#define MSC01E_INT_BASE 64
+#define MSC01E_INT_BASE 96

/* SOC-it EIC interrupt offsets */
#define MSC01E_INT_SW0 1
--
2.1.0.rc2.206.gedb03e5


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